? semiconductor components industries, llc, 2001 october, 2001 rev. 7 1 publication order number: sn74ls257b/d sn74ls257b, sn74ls258b quad 2-input multiplexer with 3-state outputs the lsttl/msi sn74ls257b and the sn74ls258b are quad 2-input multiplexers with 3-state outputs. four bits of data from two sources can be selected using a common data select input. the four outputs present the selected data in true (non-inverted) form. the outputs may be switched to a high impedance state with a high on the common output enable (e o ) input, allowing the outputs to interface directly with bus oriented systems. it is fabricated with the schottky barrier diode process for high speed and is completely compatible with all on semiconductor ttl families. ? schottky process for high speed ? multiplexer expansion by tying outputs together ? non-inverting 3-state outputs ? input clamp diodes limit high speed termination effects ? special circuitry ensures glitch free multiplexing ? esd > 3500 volts guaranteed operating ranges symbol parameter min typ max unit v cc supply voltage 4.75 5.0 5.25 v t a operating ambient temperature range 0 25 70 c i oh output current high 2.6 ma i ol output current low 24 ma low power schottky soeiaj m suffix case 966 16 1 device package shipping ordering information sn74ls257bn 16 pin dip 2000 units/box sn74ls257bd soic16 38 units/rail sn74ls257bdr2 soic16 2500/tape & reel sn74ls257bm soeiaj16 see note 1 sn74ls257bmel soeiaj16 1. for ordering information on the eiaj version of the soic package, please contact your local on semiconductor representative. see note 1 http://onsemi.com 16 pin dip 2000 units/box sn74ls258bd soic16 38 units/rail sn74ls258bdr2 soic16 2500/tape & reel sn74ls258bm soeiaj16 see note 1 sn74ls258bmel soeiaj16 see note 1 sn74ls258bn soic d suffix case 751b plastic n suffix case 648 16 1 16 1
sn74ls257b, sn74ls258b http://onsemi.com 2 connection diagram dip (top view) note: the flatpak version has the same pinouts (connection diagram) as the dual inline package. 14 13 12 11 10 9 123456 7 16 15 8 v cc s e 0 i 0c i 1c z c i 1d i 0d z d i 0a i 1a z a i 0b i 1b z b gnd sn74ls257b sn74ls258b v cc = pin 16 gnd = pin 8 14 13 12 11 10 9 123456 7 16 15 8 v cc s e 0 i 0c i 1c z c i 1d i 0d z d i 0a i 1a z a i 0b i 1b z b gnd
sn74ls257b, sn74ls258b http://onsemi.com 3 logic diagrams sn74ls257b e 0 i 0a i 1a i 0b i 1b i 0c i 1c i 0d i 1d s z a z b z c z d sn74ls258b v cc = pin 16 gnd = pin 8 = pin numbers e 0 i 0a i 1a i 0b i 1b i 0c i 1c i 0d i 1d s z a z b z c z d 14 1 2 6 7 3 4 5 9 11 12 10 13 15 14 1 2 6 3 5 11 10 13 15 7 4 9 12
sn74ls257b, sn74ls258b http://onsemi.com 4 functional description the ls257b and ls258b are quad 2-input multiplexers with 3-state outputs. they select four bits of data from two sources each under control of a common data select input. when the select input is low, the i 0 inputs are selected and when select is high, the i 1 inputs are selected. the data on the selected inputs appears at the outputs in true (non-inverted) form for the ls257b and in the inverted form for the ls258b. the ls257b and ls258b are the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the select input. the logic equations for the outputs are shown below: when the output enable input (e 0 ) is high, the outputs are forced to a high impedance aoffo state. if the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. designers should ensure that output enable signals to 3-state devices whose outputs are tied together are designed so there is no overlap. ls257b z a = e 0 ? (i 1a ? s + i 0a ? s ) z b = e 0 ? (i 1b ? s + i 0b ? s ) z c = e 0 ? (i 1c ? s + i 0c ? s ) z d = e 0 ? (i 1d ? s + i 0d ? s ) ls258b z a = e 0 ? (i 1a ? s + i 0a ? s ) z b = e 0 ? (i 1b ? s + i 0b ? s ) z c = e 0 ? (i 1c ? s + i 0c ? s ) z d = e 0 ? (i 1d ? s + i 0d ? s ) truth table output enable select input data inputs outputs ls257b outputs ls258b e o s i 0 i 1 z z h x x x (z) (z) l h x ll h l h x hh l l l l xl h l l h x h l h = high voltage level l = low voltage level x = don't care (z) = high impedance (off)
sn74ls257b, sn74ls258b http://onsemi.com 5 dc characteristics over operating temperature range (unless otherwise specified) limits symbol parameter min typ max unit test conditions v ih input high voltage 2.0 v guaranteed input high voltage for all inputs v il input low voltage 0.8 v guaranteed input low voltage for all inputs v ik input clamp diode voltage 0.65 1.5 v v cc = min, i in = 18 ma v oh output high voltage 2.4 3.1 v v cc = min, i oh = max, v in = v ih or v il per truth table v ol out p ut low voltage 0.25 0.4 v i ol = 12 ma v cc = v cc min, v in v il or v ih v ol output low voltage 0.35 0.5 v i ol = 24 ma v in = v il or v ih per truth table i ozh output off current e high 20 m a v cc = max, v out = 2.7 v i ozl output off current e low 20 m a v cc = max, v out = 0.4 v i ih input high current other inputs s inputs 20 40 m a v cc = max, v in = 2.7 v i ih other inputs s inputs 0.1 0.2 ma v cc = max, v in = 7.0 v i il input low current all inputs 0.4 ma v cc = max, v in = 0.4 v i os short circuit current (note 2) 30 130 ma v cc = max power supply current total, output high ls257b ls258b 10 9.0 ma i cc total, output low ls257b ls258b 16 14 ma v cc = max total, output 3-state ls257b ls258b 19 16 ma 2. not more than one output should be shorted at a time, nor for more than 1 second. ac characteristics (t a = 25 c, v cc = 5.0 v) see sn74ls251 for waveforms limits symbol parameter min typ max unit test conditions t plh t phl propagation delay, data to output 10 12 13 15 ns figures 1 & 2 c l =45 p f t plh t phl propagation delay, select to output 14 14 21 21 ns figures 1 & 2 c l = 45 pf t pzh output enable time to high level 20 25 ns figures 4 & 5 c l = 45 pf t pzl output enable time to low level 20 25 ns figures 3 & 5 c l = 45 f r l = 667 w t plz output disable time to low level 16 25 ns figures 3 & 5 c l = 5.0 pf t phz output disable time from high level 18 25 ns figures 4 & 5 c l = 5 . 0 f r l = 667 w
sn74ls257b, sn74ls258b http://onsemi.com 6 package dimensions n suffix plastic package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
sn74ls257b, sn74ls258b http://onsemi.com 7 package dimensions d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
sn74ls257b, sn74ls258b http://onsemi.com 8 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z m suffix soeiaj package case 96601 issue o on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. sn74ls257b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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